Fabrication Process for Co-Fabricating a Multilayer Probe Array and a Space Transformer

ABSTRACT

Embodiments of the invention provide electrochemical fabrication processes that may be used for the fabrication of space transformers or the co-fabrication of microprobe arrays along with one or more space transformers.

RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.11/028,945 (Microfabrica Docket No. P-US134-A-MF), filed Jan. 3, 2005,which claims benefit of U.S. Provisional Patent Application Nos.60/533,948 and 60/574,737, filed Dec. 31, 2003 and May 26, 2003,respectively. These applications are hereby incorporated herein byreference as if set forth in full herein.

FIELD OF THE INVENTION

The present invention relates generally to the field of electrochemicalfabrication and the associated formation of three-dimensional structures(e.g. microscale or mesoscale structures). In particular, it relates toelectrochemical fabrication methods for fabricating space transformersand microprobes.

BACKGROUND OF THE INVENTION

A technique for forming three-dimensional structures (e.g. parts,components, devices, and the like) from a plurality of adhered layerswas invented by Adam L. Cohen and is known as ElectrochemicalFabrication. It is being commercially pursued by Microfabrica Inc.(formerly MEMGen Corporation) of Van Nuys, Calif. under the name EFAB®.This technique was described in U.S. Pat. No. 6,027,630, issued on Feb.22, 2000. This electrochemical deposition technique allows the selectivedeposition of a material using a unique masking technique that involvesthe use of a mask that includes patterned conformable material on asupport structure that is independent of the substrate onto whichplating will occur. When desiring to perform an electrodeposition usingthe mask, the conformable portion of the mask is brought into contactwith a substrate while in the presence of a plating solution such thatthe contact of the conformable portion of the mask to the substrateinhibits deposition at selected locations. For convenience, these masksmight be generically called conformable contact masks; the maskingtechnique may be generically called a conformable contact mask platingprocess. More specifically, in the terminology of Microfabrica Inc.(formerly MEMGen Corporation) of Van Nuys, Calif. such masks have cometo be known as INSTANT MASKS™ and the process known as INSTANT MASKING™or INSTANT MASKING™ plating. Selective depositions using conformablecontact mask plating may be used to form single layers of material ormay be used to form multi-layer structures. The teachings of the '630patent are hereby incorporated herein by reference as if set forth infull herein. Since the filing of the patent application that led to theabove noted patent, various papers about conformable contact maskplating (i.e. INSTANT MASKING™) and electrochemical fabrication havebeen published:

-   (1) A. Cohen, G. Zhang, F. Tseng, F. Mansfeld, U. Frodis and P.    Will, “EFAB: Batch production of functional, fully-dense metal parts    with micro-scale features”, Proc. 9th Solid Freeform Fabrication,    The University of Texas at Austin, p 161, August 1998.-   (2) A. Cohen, G. Zhang, F. Tseng, F. Mansfeld, U. Frodis and P.    Will, “EFAB: Rapid, Low-Cost Desktop Micromachining of High Aspect    Ratio True 3-D MEMS”, Proc. 12th IEEE Micro Electro Mechanical    Systems Workshop, IEEE, p 244, January 1999.-   (3) A. Cohen, “3-D Micromachining by Electrochemical Fabrication”,    Micromachine Devices, March 1999.-   (4) G. Zhang, A. Cohen, U. Frodis, F. Tseng, F. Mansfeld, and P.    Will, “EFAB: Rapid Desktop Manufacturing of True 3-D    Microstructures”, Proc. 2nd International Conference on Integrated    MicroNanotechnology for Space Applications, The Aerospace Co., April    1999.-   (5) F. Tseng, U. Frodis, G. Zhang, A. Cohen, F. Mansfeld, and P.    Will, “EFAB: High Aspect Ratio, Arbitrary 3-D Metal Microstructures    using a Low-Cost Automated Batch Process”, 3rd International    Workshop on High Aspect Ratio MicroStructure Technology (HARMST'99),    June 1999.-   (6) A. Cohen, U. Frodis, F. Tseng, G. Zhang, F. Mansfeld, and P.    Will, “EFAB: Low-Cost, Automated Electrochemical Batch Fabrication    of Arbitrary 3-D Microstructures”, Micromachining and    Microfabrication Process Technology, SPIE 1999 Symposium on    Micromachining and Microfabrication, September 1999.-   (7) F. Tseng, G. Zhang, U. Frodis, A. Cohen, F. Mansfeld, and P.    Will, “EFAB: High Aspect Ratio, Arbitrary 3-D Metal Microstructures    using a Low-Cost Automated Batch Process”, MEMS Symposium, ASME 1999    International Mechanical Engineering Congress and Exposition,    November, 1999.-   (8) A. Cohen, “Electrochemical Fabrication (EFAB™)”, Chapter 19 of    The MEMS Handbook, edited by Mohamed Gad-El-Hak, CRC Press, 2002.-   (9) Microfabrication—Rapid Prototyping's Killer Application”, pages    1-5 of the Rapid Prototyping Report, CAD/CAM Publishing, Inc., June    1999.

The disclosures of these nine publications are hereby incorporatedherein by reference as if set forth in full herein.

The electrochemical deposition process may be carried out in a number ofdifferent ways as set forth in the above patent and publications. In oneform, this process involves the execution of three separate operationsduring the formation of each layer of the structure that is to beformed:

-   -   (1) Selectively depositing at least one material by        electrodeposition upon one or more desired regions of a        substrate.    -   (2) Then, blanket depositing at least one additional material by        electrodeposition so that the additional deposit covers both the        regions that were previously selectively deposited onto, and the        regions of the substrate that did not receive any previously        applied selective depositions.    -   (3) Finally, planarizing the materials deposited during the        first and second operations to produce a smoothed surface of a        first layer of desired thickness having at least one region        containing the at least one material and at least one region        containing at least the one additional material.

After formation of the first layer, one or more additional layers may beformed adjacent to the immediately preceding layer and adhered to thesmoothed surface of that preceding layer. These additional layers areformed by repeating the first through third operations one or more timeswherein the formation of each subsequent layer treats the previouslyformed layers and the initial substrate as a new and thickeningsubstrate.

Once the formation of all layers has been completed, at least a portionof at least one of the materials deposited is generally removed by anetching process to expose or release the three-dimensional structurethat was intended to be formed.

The preferred method of performing the selective electrodepositioninvolved in the first operation is by conformable contact mask plating.In this type of plating, one or more conformable contact (CC) masks arefirst formed. The CC masks include a support structure onto which apatterned conformable dielectric material is adhered or formed. Theconformable material for each mask is shaped in accordance with aparticular cross-section of material to be plated. At least one CC maskis needed for each unique cross-sectional pattern that is to be plated.

The support for a CC mask is typically a plate-like structure formed ofa metal that is to be selectively electroplated and from which materialto be plated will be dissolved. In this typical approach, the supportwill act as an anode in an electroplating process. In an alternativeapproach, the support may instead be a porous or otherwise perforatedmaterial through which deposition material will pass during anelectroplating operation on its way from a distal anode to a depositionsurface. In either approach, it is possible for CC masks to share acommon support, i.e. the patterns of conformable dielectric material forplating multiple layers of material may be located in different areas ofa single support structure. When a single support structure containsmultiple plating patterns, the entire structure is referred to as the CCmask while the individual plating masks may be referred to as“submasks”. In the present application such a distinction will be madeonly when relevant to a specific point being made.

In preparation for performing the selective deposition of the firstoperation, the conformable portion of the CC mask is placed inregistration with and pressed against a selected portion of thesubstrate (or onto a previously formed layer or onto a previouslydeposited portion of a layer) on which deposition is to occur. Thepressing together of the CC mask and substrate occur in such a way thatall openings, in the conformable portions of the CC mask contain platingsolution. The conformable material of the CC mask that contacts thesubstrate acts as a barrier to electrodeposition while the openings inthe CC mask that are filled with electroplating solution act as pathwaysfor transferring material from an anode (e.g. the CC mask support) tothe non-contacted portions of the substrate (which act as a cathodeduring the plating operation) when an appropriate potential and/orcurrent are supplied.

An example of a CC mask and CC mask plating are shown in FIGS. 1A-1C.FIG. 1A shows a side view of a CC mask 8 consisting of a conformable ordeformable (e.g. elastomeric) insulator 10 patterned on an anode 12. Theanode has two functions. FIG. 1A also depicts a substrate 6 separatedfrom mask 8. One is as a supporting material for the patterned insulator10 to maintain its integrity and alignment since the pattern may betopologically complex (e.g., involving isolated “islands” of insulatormaterial). The other function is as an anode for the electroplatingoperation. CC mask plating selectively deposits material 22 onto asubstrate 6 by simply pressing the insulator against the substrate thenelectrodepositing material through apertures 26 a and 26 b in theinsulator as shown in FIG. 1B. After deposition, the CC mask isseparated, preferably non-destructively, from the substrate 6 as shownin FIG. 1C. The CC mask plating process is distinct from a“through-mask” plating process in that in a through-mask plating processthe separation of the masking material from the substrate would occurdestructively. As with through-mask plating, CC mask plating depositsmaterial selectively and simultaneously over the entire layer. Theplated region may consist of one or more isolated plating regions wherethese isolated plating regions may belong to a single structure that isbeing formed or may belong to multiple structures that are being formedsimultaneously. In CC mask plating as individual masks are notintentionally destroyed in the removal process, they may be usable inmultiple plating operations.

Another example of a CC mask and CC mask plating is shown in FIGS.1D-1F. FIG. 1D shows an anode 12′ separated from a mask 8′ that includesa patterned conformable material 10′ and a support structure 20. FIG. 1Dalso depicts substrate 6 separated from the mask 8′. FIG. 1E illustratesthe mask 8′ being brought into contact with the substrate 6. FIG. 1Fillustrates the deposit 22′ that results from conducting a current fromthe anode 12′ to the substrate 6. FIG. 1G illustrates the deposit 22′ onsubstrate 6 after separation from mask 8′. In this example, anappropriate electrolyte is located between the substrate 6 and the anode12′ and a current of ions coming from one or both of the solution andthe anode are conducted through the opening in the mask to the substratewhere material is deposited. This type of mask may be referred to as ananodeless INSTANT MASK™ (AIM) or as an anodeless conformable contact(ACC) mask.

Unlike through-mask plating, CC mask plating allows CC masks to beformed completely separate from the fabrication of the substrate onwhich plating is to occur (e.g. separate from a three-dimensional (3D)structure that is being formed). CC masks may be formed in a variety ofways, for example, a photolithographic process may be used. All maskscan be generated simultaneously, prior to structure fabrication ratherthan during it. This separation makes possible a simple, low-cost,automated, self-contained, and internally-clean “desktop factory” thatcan be installed almost anywhere to fabricate 3D structures, leaving anyrequired clean room processes, such as photolithography to be performedby service bureaus or the like.

An example of the electrochemical fabrication process discussed above isillustrated in FIGS. 2A-2F. These figures show that the process involvesdeposition of a first material 2 which is a sacrificial material and asecond material 4 which is a structural material. The CC mask 8, in thisexample, includes a patterned conformable material (e.g. an elastomericdielectric material) 10 and a support 12 which is made from depositionmaterial 2. The conformal portion of the CC mask is pressed againstsubstrate 6 with a plating solution 14 located within the openings 16 inthe conformable material 10. An electric current, from power supply 18,is then passed through the plating solution 14 via (a) support 12 whichdoubles as an anode and (b) substrate 6 which doubles as a cathode. FIG.2A, illustrates that the passing of current causes material 2 within theplating solution and material 2 from the anode 12 to be selectivelytransferred to and plated on the cathode 6. After electroplating thefirst deposition material 2 onto the substrate 6 using CC mask 8, the CCmask 8 is removed as shown in FIG. 2B. FIG. 2C depicts the seconddeposition material 4 as having been blanket-deposited (i.e.non-selectively deposited) over the previously deposited firstdeposition material 2 as well as over the other portions of thesubstrate 6. The blanket deposition occurs by electroplating from ananode (not shown), composed of the second material, through anappropriate plating solution (not shown), and to the cathode/substrate6. The entire two-material layer is then planarized to achieve precisethickness and flatness as shown in FIG. 2D. After repetition of thisprocess for all layers, the multi-layer structure 20 formed of thesecond material 4 (i.e. structural material) is embedded in firstmaterial 2 (i.e. sacrificial material) as shown in FIG. 2E. The embeddedstructure is etched to yield the desired device, i.e. structure 20, asshown in FIG. 2F.

Various components of an exemplary manual electrochemical fabricationsystem 32 are shown in FIGS. 3A-3C. The system 32 consists of severalsubsystems 34, 36, 38, and 40. The substrate holding subsystem 34 isdepicted in the upper portions of each of FIGS. 3A to 3C and includesseveral components: (1) a carrier 48, (2) a metal substrate 6 onto whichthe layers are deposited, and (3) a linear slide 42 capable of movingthe substrate 6 up and down relative to the carrier 48 in response todrive force from actuator 44. Subsystem 34 also includes an indicator 46for measuring differences in vertical position of the substrate whichmay be used in setting or determining layer thicknesses and/ordeposition thicknesses. The subsystem 34 further includes feet 68 forcarrier 48 which can be precisely mounted on subsystem 36.

The CC mask subsystem 36 shown in the lower portion of FIG. 3A includesseveral components: (1) a CC mask 8 that is actually made up of a numberof CC masks (i.e. submasks) that share a common support/anode 12, (2)precision X-stage 54, (3) precision Y-stage 56, (4) frame 72 on whichthe feet 68 of subsystem 34 can mount, and (5) a tank 58 for containingthe electrolyte 16. Subsystems 34 and 36 also include appropriateelectrical connections (not shown) for connecting to an appropriatepower source for driving the CC masking process.

The blanket deposition subsystem 38 is shown in the lower portion ofFIG. 3B and includes several components: (1) an anode 62, (2) anelectrolyte tank 64 for holding plating solution 66, and (3) frame 74 onwhich the feet 68 of subsystem 34 may sit. Subsystem 38 also includesappropriate electrical connections (not shown) for connecting the anodeto an appropriate power supply for driving the blanket depositionprocess.

The planarization subsystem 40 is shown in the lower portion of FIG. 3Cand includes a lapping plate 52 and associated motion and controlsystems (not shown) for planarizing the depositions.

Another method for forming microstructures from electroplated metals(i.e. using electrochemical fabrication techniques) is taught in U.S.Pat. No. 5,190,637 to Henry Guckel, entitled “Formation ofMicrostructures by Multiple Level Deep X-ray Lithography withSacrificial Metal layers”. This patent teaches the formation of metalstructure utilizing mask exposures. A first layer of a primary metal iselectroplated onto an exposed plating base to fill a void in aphotoresist, the photoresist is then removed and a secondary metal iselectroplated over the first layer and over the plating base. Theexposed surface of the secondary metal is then machined down to a heightwhich exposes the first metal to produce a flat uniform surfaceextending across the both the primary and secondary metals. Formation ofa second layer may then begin by applying a photoresist layer over thefirst layer and then repeating the process used to produce the firstlayer. The process is then repeated until the entire structure is formedand the secondary metal is removed by etching. The photoresist is formedover the plating base or previous layer by casting and the voids in thephotoresist are formed by exposure of the photoresist through apatterned mask via X-rays or UV radiation.

Even though electrochemical fabrication as taught and practiced to date,has greatly enhanced the capabilities of microfabrication, and inparticular added greatly to the number of metal layers that can beincorporated into a structure and to the speed and simplicity in whichsuch structures can be made, room for enhancing the state ofelectrochemical fabrication exists as well as for adding to the types ofdevices that can be formed or co-fabricated with other devices.

SUMMARY OF THE INVENTION

It is an object of some embodiments of the invention to provide aprocess for forming space transformers using electrochemical fabricationmethods.

It is an object of some embodiments of the invention to provide aprocess for forming space transformers and microprobes in the same buildprocess

Other objects and advantages of various embodiments of the inventionwill be apparent to those of skill in the art upon review of theteachings herein. The various embodiments of the invention, set forthexplicitly herein or otherwise ascertained from the teachings herein,may address one or more objects alone or in combination, oralternatively may address some other object of the invention ascertainedfrom the teachings herein. It is not necessarily intended that allobjects be addressed by any single aspect of the invention even thoughthat may be the case with regard to some aspects.

In a first aspect of the invention, a fabrication process forco-fabricating a multi-layer probe array and a space transformer,includes: (a) forming and adhering a layer of material to a previouslyformed layer and/or to a substrate, wherein the layer comprises adesired pattern of at least one material; and (b) repeating the formingand adhering operation of (a) a plurality of times to build up an arrayof probes and a space transformer from a plurality of adhered layers,and wherein at least a portion of the plurality of layers comprises atleast one structural material and at least one sacrificial material; and(c) after formation of at least a plurality of layers, subjecting themulti-layer structure to a release process that removes at least aportion of at least one sacrificial material from at least some portionsof some layers, wherein the space transformer comprise a plurality ofinterconnect elements that connect on one side to probes that have afirst averaged spacing and connect to pads on another side that have asecond averaged spacing that is greater than the first averaged spacing.

In a second aspect of the invention, a fabrication process forfabricating a multi-layer space transformer, comprises: (a) forming andadhering a layer of material to a previously formed layer and/or to asubstrate, wherein the layer comprises a desired pattern of at least onematerial; and (b) repeating the forming and adhering operation of (a) aplurality of times to build up configuration of conductive interconnectelements in a configuration of a desired space transformer, wherein theplurality of layers are adhered to one another and comprise at least oneof (i) at least one structural material and at least one sacrificialmaterial or (ii) at least two structural materials one of which is aconductor and one of which is a dielectric.

In a specific variation of the second aspect of the invention the spacetransformer includes metal electrodeposited or electroless deposited ona layer by layer basis where the height of at least some layers is setby a planarization operation that planarizes an interconnect materialand at least one other material.

In a specific variation of the second aspect of the invention the spacetransformer includes vias and traces that coexist on at least somelayers.

In a specific variation of the second aspect of the invention the spacetransformer includes at least one more coaxial interconnects.

In a specific variation of the second aspect of the invention the spacetransformer includes interconnects having traces having at least twodifferent widths.

In a specific variation of the second aspect of the invention the spacetransformer includes interconnects comprising vias that have at leasttwo different widths.

In a specific variation of the second aspect of the invention the spacetransformer includes interconnects have trace thicknesses that are atleast as thick as some planarized thicknesses of a dielectric material.

In a specific variation of the second aspect of the invention the spacetransformer includes interconnects have trace thicknesses that are atleast as thick as the differential height between some interconnecttraces.

In a specific variation of the second aspect of the invention at leastone layer of the space transformer is formed using a process comprising:patterning a first material, applying a non-planar seed layer,electrodepositing a second material, and trimming off at least a portionof the deposited first material.

In a third aspect of the invention, a space transformer includes aplurality of interconnect elements that are connectable on one side toprobes that have a first averaged spacing and connectable on a differentside to pads that have a second averaged spacing that is greater thanthe first averaged spacing.

In a specific variation of the third aspect of the invention the spacetransformer includes metal electrodeposited or electroless deposited ona layer by layer basis where the height of at least some layers is setby a planarization operation that planarizes an interconnect materialand at least one other material.

In a specific variation of the third aspect of the invention the spacetransformer includes vias and traces that coexist on at least somelayers.

In a specific variation of the third aspect of the invention the spacetransformer includes at least one more coaxial interconnects.

In a specific variation of the third aspect of the invention the spacetransformer includes interconnects having traces having at least twodifferent widths.

In a specific variation of the third aspect of the invention the spacetransformer includes interconnects comprising vias that have at leasttwo different widths.

In a specific variation of the third aspect of the invention the spacetransformer includes interconnects have trace thicknesses that are atleast as thick as some planarized thicknesses of a dielectric material.

In a specific variation of the third aspect of the invention the spacetransformer includes interconnects have trace thicknesses that are atleast as thick as the differential height between some interconnecttraces.

Further aspects of the invention will be understood by those of skill inthe art upon reviewing the teachings herein. Other aspects of theinvention may involve apparatus that can be used in implementing one ormore of the above method aspects of the invention. These other aspectsof the invention may provide various combinations of the aspects,embodiments, and associated alternatives explicitly set forth herein aswell as provide other configurations, structures, functionalrelationships, and processes that have not been specifically set forthabove.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1C schematically depict side views of various stages of a CCmask plating process, while FIGS. 1D-G schematically depict a side viewsof various stages of a CC mask plating process using a different type ofCC mask.

FIGS. 2A-2F schematically depict side views of various stages of anelectrochemical fabrication process as applied to the formation of aparticular structure where a sacrificial material is selectivelydeposited while a structural material is blanket deposited.

FIGS. 3A-3C schematically depict side views of various examplesubassemblies that may be used in manually implementing theelectrochemical fabrication method depicted in FIGS. 2A-2F.

FIGS. 4A-4I schematically depict the formation of a first layer of astructure using adhered mask plating where the blanket deposition of asecond material overlays both the openings between deposition locationsof a first material and the first material itself.

FIGS. 5A-5J schematically depict side views of various stages in aprocess for forming a space transformer from a conductive structuralmaterial and from a conductive sacrificial material which may bereplaced by a dielectric material.

FIGS. 6A-6L schematically depict side views of various stages in aprocess for forming a space transformer from a conductive structuralmaterial and from a conductive sacrificial material wherein a dielectriclid is formed over the structure and the sacrificial material is removedwhich may be replaced by a dielectric material.

FIGS. 7A-7F schematically depict side views of various stages in aprocess for forming a space transformer from a conductive structuralmaterial and from a dielectric structural material that is also apatterning material.

FIGS. 8A-8I schematically depict side views of various stages in aprocess for forming a space transformer from a conductive structuralmaterial and from a dielectric structural material that is not apatterning material.

FIGS. 9A-9O schematically depict side views of various stages in aprocess for forming a space transformer, including formation andmaintenance of substrate end pointing regions from a conductivestructural material and a conductive sacrificial material which isremoved and may be replaced by a dielectric material.

FIGS. 10A-10C provide side views of three simplified interconnectconfigurations that may be used in a space transformer.

FIGS. 11A-11L provide schematic side views of various states in aprocess of forming a coaxial space transformer.

FIG. 12 provides a schematic side view of an alternative technique forshielding sidewalls of a space transformer.

FIGS. 13A-13X depict schematic representations of side views of variousstates of a process according to a first embodiment of the inventionwhich calls for the co-fabrication of a set of microprobes and a spacetransformer.

FIGS. 14A-14G provide various perspective, side and close up views of anexemplary space transformer and probe array that may be formed with someembodiments of the invention wherein the space transformer is shown asfree standing (i.e. not encapsulated in a dielectric).

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS OF THE INVENTION

FIGS. 1A-1G, 2A-2F, and 3A-3C illustrate various features of one form ofelectrochemical fabrication that are known. Other electrochemicalfabrication techniques are set forth in the '630 patent referencedabove, in the various previously incorporated publications, in variousother patents and patent applications incorporated herein by reference,still others may be derived from combinations of various approachesdescribed in these publications, patents, and applications, or areotherwise known or ascertainable by those of skill in the art from theteachings set forth herein. All of these techniques may be combined withthose of the various embodiments of various aspects of the invention toyield enhanced embodiments. Still other embodiments may be derived fromcombinations of the various embodiments explicitly set forth herein.

FIGS. 4A-4I illustrate various stages in the formation of a single layerof a multi-layer fabrication process where a second metal is depositedon a first metal as well as in openings in the first metal where itsdeposition forms part of the layer. In FIG. 4A, a side view of asubstrate 82 is shown, onto which patternable photoresist 84 is cast asshown in FIG. 4B. In FIG. 4C, a pattern of resist is shown that resultsfrom the curing, exposing, and developing of the resist. The patterningof the photoresist 84 results in openings or apertures 92(a)-92(c)extending from a surface 86 of the photoresist through the thickness ofthe photoresist to surface 88 of the substrate 82. In FIG. 4D, a metal94 (e.g. nickel) is shown as having been electroplated into the openings92(a)-92(c). In FIG. 4E, the photoresist has been removed (i.e.chemically stripped) from the substrate to expose regions of thesubstrate 82 which are not covered with the first metal 94. In FIG. 4F,a second metal 96 (e.g., silver) is shown as having been blanketelectroplated over the entire exposed portions of the substrate 82(which is conductive) and over the first metal 94 (which is alsoconductive). FIG. 4G depicts the completed first layer of the structurewhich has resulted from the planarization of the first and second metalsdown to a height that exposes the first metal and sets a thickness forthe first layer. In FIG. 4H the result of repeating the process stepsshown in FIGS. 4B-4G several times to form a multi-layer structure areshown where each layer consists of two materials. For most applications,one of these materials is removed as shown in FIG. 4I to yield a desired3-D structure 98 (e.g. component or device).

The various embodiments, alternatives, and techniques disclosed hereinmay form multi-layer structures using a single patterning technique onall layers or using different patterning techniques on different layers.For example, different types of patterning masks and masking techniquesmay be used or even techniques that perform direct selective depositionswithout the need for masking. For example, conformable contact masks maybe used on some layers while nonconformable contact masks and maskingoperations may be used on other layers. Proximity masks and maskingoperations (i.e. operations that use masks that at least partiallyselectively shield a substrate by their proximity to the substrate evenif contact is not made) may be used, and adhered masks and maskingoperations (masks and operations that use masks that are adhered to asubstrate onto which selective deposition or etching is to occur asopposed to only being contacted to it) may be used.

FIGS. 5A-5J schematically depict side views of various stages in aprocess for forming a space transformer from a conductive structuralmaterial and from a conductive sacrificial material which may bereplaced by a dielectric material. After formation, the substrate sideof the space transformer may be bonded to a printed circuit board aninterposer or other electrical component while the other side of thespace transformer may have probes formed thereon or mounted thereto.

FIG. 5A depicts the state of the process after a dielectric (e.g.,alumina) substrate 102 is supplied having an array of relatively coarseconductive vias 104 which are composed of a metal that connects the top108 and bottom surfaces 106 of the substrate. The vias are shownproceeding straight from the bottom surface 106 of the substrate to thetop surface 108. In some variations of this embodiment, a circuitousroute may be taken by the vias. This embodiment of the invention uses a‘standard’ via substrate having vias in an array at a specific,relatively coarse pitch that is compatible with printed circuit board(PCB) line widths. The customization offered by the present embodiment,is accomplished entirely by the deposited layers of material. Typicallysome vias through the substrate will be used while others will remainunused depending on the specific layout of a particular spacetransformer. The substrate of the present embodiment is thick and rigidenough to be self-supporting, while in variations of this embodiment thesubstrate may be flexible. Since the total thickness of the layers to bedeposited is typically only on the order of several hundred microns, thesubstrate provides the rigidity and robustness required for mounting thefinal space transformer and microprobe combination onto a PCB. Asindicated, the substrate is metallized by deposition of a metal film 110(e.g., by sputtering). The metal film 110 serves as a seed layer and mayalso serve as an adhesion layer (if necessary), possibly as a barrierlayer and/or as a transition layer. In some embodiments the metal film110 may actually comprise two or more individually applied layers, forexample, the film may include an adhesion layer of, e.g., Ti, and a seedlayer of, e.g., Au.

In FIG. 5B, a photoresist 112 has been applied and patterned and a firstlayer of structural material 114 (e.g. Ni) has been pattern-plated. Insome alternative embodiments, sacrificial material may be pattern platedand then structural material may be blanket-plated, and then the layerplanarized. Electrical contact (i.e. cathodic contact) may be made viathe metal film 110.

In FIG. 5C, the resist has been stripped and the exposed portion ofmetal film 110 etched back. The portion of the film located under thedeposited structural material 114 is not removed as it is not readilyaccessible.

In FIG. 5D, a seed layer of sacrificial material 118 (e.g. Cu) has beendeposited by PVD (e.g., sputtering). This seed layer serves as a cathodefor subsequent plating and may be used as the contact point forconnecting to an electric circuit or alternatively some other conductiveelement connected to the seed layer may be used as the circuit contactpoint.

In FIG. 5E, a sacrificial material 124, e.g. Cu, has been thickly plated(e.g. at greater than a desired layer thickness).

In FIG. 5F the build has been planarized, completing the first layer.Building is then allowed to continue so that additional layers areformed so long as both structural and sacrificial materials areconductive there is no need to apply seed layers during formation of the2^(nd)-N^(th) layers. If one of the materials is non-conductiveformation of some or all layers may require use of one or more seedlayers.

In FIG. 5G, all the layers of the space transformer have been completedwith three-dimensional structural material 114 interconnect beingembedded in sacrificial material 124 and laid out in a pattern thatconnects the relatively coarse-pitch vias to the relatively fine-pitchprobes or other devices which may be formed on or bonded to the spacetransformer.

In FIG. 5H, the exposed sacrificial material has been removed to releasethe interconnect lines of the space transformer. The removal of thesacrificial material may occur by immersing the entire build intosacrificial material etchant. Following etching of the sacrificialmaterial, diffusion bonding (e.g., at 250° C.) may be performed toimprove the inter-layer adhesion of the layers of structural material.More teaching concerning the use of diffusion bonding in electrochemicalfabrication processes may be found in U.S. patent application Ser. No.10/841,384 which is filed May 7, 2004 by Cohen et al. which is entitled“Method of Electrochemically Fabricating Multilayer Structures HavingImproved Interlayer Adhesion” and which is hereby incorporated herein byreference as if set forth in full.

In some variations of the present embodiment, solder bumps may belocated on the under side of the substrate to aid mounting of the spacetransformer to a circuit board or the like. In still other embodimentssolder bumps may be located on the ends of the interconnect elements inpreparation for bonding probes or other components to the spacetransformer. In still other embodiments diffusion bonding may occurprior to the release of FIG. 5H. In some embodiments, the release of theinterconnect elements from the sacrificial material may completeformation of the space transformer as it is intended that theinterconnect elements be free standing. In still other embodiments theinterconnect elements may not be free standing but instead be embeddedin a dielectric material. FIG. 5I depicts the state of the process aftersuch an embedment occurs while FIG. 5J depicts the state of the processafter a planarization operation removes any excess dielectric from abovethe interconnect elements formed of material 114.

FIGS. 6A-6L schematically depict side views of various stages in aprocess for forming a space transformer from a conductive structuralmaterial and from a conductive sacrificial material wherein a dielectriclid is formed over the structure and the sacrificial material is removedwhich may be replaced by a dielectric material.

FIGS. 6A-6G are identical to FIGS. 5A-5G with the exception that thebuilding of layers of the space transformer are not complete after theprocessing that lead to FIG. 6G.

In FIG. 6H, structural material 114 has been pattern-plated to form whatwill become fine-pitch vias which will extend through an insulatinglayer that will next be fabricated. The pattern plating may occur in avariety of ways, such as by use of a temporarily placed and patternedphotoresist that is removed after plating of material 114.

In FIG. 6I a high-temperature resistant dielectric material 128 (e.g.,polyimide, glass, or the like) has been applied and (if needed) cured.

In FIG. 6J the state of the process is shown after a planarizationoperation has removed excess dielectric material 128 and set the heightsof materials 114 and 128 to a desired common level. The planarizationoperation removes the dielectric that lays over the structural materialand leaves in place a dielectric layer that will form a ‘roof’ for thespace transformer.

In FIG. 6K, like in FIG. 5H, the exposed sacrificial material has beenremoved to release the interconnect lines of the space transformer. Aswith the above discussion of FIG. 5H, diffusion bonding may occur beforeor after release of the structure or it may not occur at all.

In some variations of the present embodiment, solder bumps may belocated on the under side of the substrate to aid mounting of the spacetransformer to a circuit board or the like. In still other embodimentssolder bumps may be located on the ends of the interconnect elementsexposed through the top of dielectric material 128 in preparation forbonding probes or other components to the space transformer. In someembodiments, the release of the interconnect elements from thesacrificial material may complete formation of the space transformer asit is intended that the interconnect elements be free standing with someadded support offered by the dielectric material 128 that caps the spacetransformer. In still other embodiments the interconnect elements maynot be free standing but instead be embedded in a dielectric material.FIG. 6L depicts the state of the process after such an embedment occurs.

FIGS. 7A-7F schematically depict side views of various stages in aprocess for forming a space transformer from a conductive structuralmaterial and from a dielectric structural material that is also apatterning material. The build process of FIGS. 7A-7F are based on theuse of non-planar seed layers as taught in U.S. patent application Ser.No. 10/841,300 which is hereby incorporated herein by reference.

FIG. 7A depicts the state of the process after a substrate 102 issupplied. As with FIGS. 5 and 6, substrate 102 contains vias 104 thatextend from a lower surface of the substrate to an upper surface of thesubstrate.

FIG. 7B depicts a state of the process after a dielectric 112 is placedon the upper surface of the substrate and is patterned. The patterningof the dielectric material may occur before or after locating thematerial on the substrate. In some embodiments the dielectric material112 may be a photoresist.

FIG. 7C depicts the state of the process after a seed layer 110 isdeposited over the dielectric material 112 and into the voids oropenings that extend through the dielectric material.

FIG. 7D depicts a state of the process after a conductive material 114is plated over seed layer 110.

FIG. 7E depicts the state of the process after a planarization processtrims the height of the dielectric material 112, seed layer 110 andconductive material 114 to a height corresponding to the layer thicknessLT. FIG. 7E depicts a state of the process after formation of the firstlayer is completed.

FIG. 7F depicts the state of the process after formation of a pluralityof layers which completes formation of the space transformer.

FIGS. 8A-8I schematically depict side views of various stages in aprocess for forming a space transformer from a conductive structuralmaterial and from a dielectric structural material that is not apatterning material.

FIG. 8A-8E are similar to FIGS. 7A-7E already discussed with theexception that the height of planarization of FIG. 8E is set at slightlymore then one layer thickness (LT+δ) as opposed to being set at thelayer thickness (LT) as in FIG. 7E.

FIG. 8F shows the state of the process after dielectric material 112 hasbeen removed.

FIG. 8G shows the state of the process after a second dielectricmaterial 113 has been applied where the application is shown in thisexample to have slightly over coated regions of structural material 114.

FIG. 8H shows the state of the process after a planarization operationtrims the height of deposited materials to that of the layer thickness.

FIG. 8I shows a similar state of the process as shown in FIG. 7F wherethe formation of the space transformer is completed and is imbedded in adesired dielectric material. In FIG. 8I the dielectric material is shownto be different from an initial dielectric material that was used forpatterning operation where as in FIG. 7F the patterning dielectric andstructural dielectrics were the same.

FIGS. 9A-9O schematically depict side views of various stages in aprocess for forming a space transformer, including formation andmaintenance of substrate end pointing regions from a conductivestructural material and a conductive sacrificial material which isremoved and may be replaced by a dielectric material.

FIG. 9A depicts the state of the process after a dielectric (e.g.,alumina) substrate 102 is supplied having an array of relatively coarseconductive vias 104 which are composed of a metal that connects the top108 and bottom surfaces106 of the substrate and on which a seed layer110 has been applied. The state of the process is similar to thatdiscussed in association with FIG. 5A.

In FIG. 9B, a photoresist 112 has been applied and patterned and a firstlayer of structural material 114 (e.g. Ni) has been pattern-plated. Thestate of the process is similar to that discussed in association withFIG. 5B.

In FIG. 9C, the resist has been stripped and the exposed portion ofmetal film 110 etched back. The portion of the film located under thedeposited structural material 114 is not removed as it is not readilyaccessible. The state of the process is similar to that discussed inassociation with FIG. 5C.

In FIG. 9D, a seed layer of sacrificial material 118 (e.g. Cu) has beendeposited by e.g. PVD (e.g. sputtering). The state of the process issimilar to that discussed in association with FIG. 5D.

In FIG. 9E, the seed layer is shown as having been etched away from anarea of an end-point detection region 122 (additional end pointdetection pads may exist on the substrate but are just not visible fromthe view provided by FIG. 9E. This removal may, for example, occur byuse of a patterned mask that is formed after which etching is allowed tooccur, and then the mask removed. This removal of the seed layerprevents metal from being plated up in this region. Of course, inpractice the end point detection region 112 will need to be wide enoughso that plating of metal occurring via a mushrooming effect from theside walls of structural material 112 which surrounds end-pointdetection pad 122 will not result in the covering of the pad. Inalternative embodiments, at the time of application of seed layer andadhesion layer material the end-point detection region may be shieldedso as to not receive the materials.

In FIG. 9F, a sacrificial material 124, e.g. Cu, has been thickly plated(e.g. at greater than a desired layer thickness). In FIG. 9G the buildhas been planarized, completing the first layer. Building is thenallowed to continue so that additional layers are formed so long as bothstructural and sacrificial materials are conductive there is no need toapply a seed layer during formation of the 2^(nd)-N^(th) layers. If oneof the materials is non-conductive formation of some or all layers mayrequire use of one or more seed layers. In FIG. 9H, all the layers ofthe space transformer portion of the build have been completed (with theexception of a capping layer) with three-dimensional structural material114 interconnect being embedded in sacrificial material 124 and laid outin a pattern that connects the relatively coarse-pitch vias to therelatively fine-pitch probes or other components which may be formed onthe space transformer or which may be bonded to the space transformerafter formation.

In FIG. 9I, structural material 114 has been pattern-plated to form whatwill become fine-pitch vias which will extend through an insulatinglayer that will next be fabricated. In FIG. 9J, a cap 126 has beenapplied over the endpoint detection region or area and ahigh-temperature resistant dielectric material 128 (e.g., polyimide,glass, or the like) has been applied and (if needed) cured.

In FIG. 9K, the cap has been removed and the build has been planarized(and if necessary the opening 132 above the end-point detection pad hasbeen cleaned of debris from the planarization operation. In someembodiments that cap may be removed as part of the planarizationoperation while in other embodiments it may be removed in a separateoperation. The planarization operation removes the dielectric that laysover the structural material vias of FIG. 9I and leaves in place adielectric layer that will form a ‘roof’ for the space transformerportion of the device.

In FIG. 9L, the exposed sacrificial material has been removed to releasethe structure. The sacrificial material may be removed by immersing theentire build into sacrificial material etchant. The release occurssubstantially in a lateral manner, with etchant flowing under the roofor cap structure 128 and around structural material interconnects andstructural material pillars 162 that may be used to support the roof ofthe space transformer (e.g., one in each corner of the device, or spacedout at intervals around the perimeter).

In some variations of the present embodiment, solder bumps may belocated on the under side of the substrate to aid mounting of the spacetransformer to a circuit board or the like. In still other embodimentssolder bumps may be located on the ends of the interconnect elementsexposed through the top of dielectric material 128 in preparation forbonding probes or other components to the space transformer. In someembodiments, the release of the interconnect elements from thesacrificial material may complete formation of the space transformer asit is intended that the interconnect elements be free standing with someadded support offered by the dielectric material 128 that caps the spacetransformer. In still other embodiments the interconnect elements maynot be free standing but instead be embedded in a dielectric material.FIG. 6L depicts the state of the process after such an embedment occurs.

In FIG. 9M, a back fill material 172 has been infiltrated into thestructure between the substrate and cap 128 and cured to fill the voidsin the space transformer. In the present embodiment the back fillmaterial is an epoxy material. In variations of the embodiment, furtherrestrictions on accessibility of the backfill material to certainregions may be implemented. Since the interconnects are fastened at bothends, it is believed that, with careful backfilling, they will be ableto resist deformation and shorting to one another during the fillingprocess.

In FIG. 9N, cap 128 has been removed via a planarization operation. Insome alternative embodiments, cap 128 could remain as part of the spacetransformer.

In FIG. 9O, the build has been diced to allow separation of individualpackage dies. After dicing, debris is removed (e.g., by megasonic orultrasonic cleaning). As shown, the dicing may leave behind a portion ofthe Ni pillars (in the transformer region), whereas in variations ofthis embodiment, the pillars may be removed in their entirety or left intheir entirety.

In some embodiments of the invention a space transform may be formedwith coaxial interconnects to allow improved signal transmission andreduced interference. The space transformer coaxial interconnects mayinclude a center conductor surrounded by a metallic shield and separatedby a dielectric (e.g. a patterned polymer). Coaxial space transformersoffer improved performance when used, for example, to probehigh-frequency semiconductors, and/or when carrying higher currents(e.g., for logic semiconductor probing). Some such embodiments areillustrated in FIGS. 10A-10C, 11A-11K, and 12.

As noted above according to some embodiments of the invention, a spacetransformer may be fabricated using a patterned polymer, a non-planarseed layer, and a plated material such as Cu. The patterned polymer maybe for example, polyimide (e.g. photopatternable polyimide such asHD-4000 from HD Microsystems), benzocyclobutene (e.g., photopatternableBCB such as Cyclotene 4000 from Dow Corning), or photoresist (e.g., SU-8from MicroChem). BCB is particularly resistant to Cu etchants, allowslower processing temperatures, and offers relative immunity to Cumigration, and allows high-frequency performance.

FIG. 10A shows a simplified space transformer 302 which has a singleinterconnect 304 that is an unshielded conductor embedded in adielectric material 310. The space transformer is built on a substrate306 that has a metal-filled (i.e., conductive) via 308.

FIG. 10B shows a coaxial space transformer 322 in which the interconnect324 is surrounded by a shield 325, and in which the shield is of roughlyconstant thickness, with its exterior surface following the path of theinterconnect.

FIG. 10C shows another embodiment of a coaxial space transformer 322′ inwhich the interconnect 324 is surrounded by shielding material 325′ ofvarying thickness. In effect, this type of space transformer is a solidblock of metal (i.e. the shield material 325′) pierced with holes, eachof which is filled with a conductor (i.e. the interconnects 324)surrounded by dielectric 330. Adjacent interconnects thus share a commonshield. In some embodiments, the shielding material may be surrounded bya dielectric material and may make contact with a ground structure.

There may be several benefits of a “solid block space transformer(SBST)” (e.g. as illustrated in FIG. 10C)’ vs. the space transformershown in FIG. 10B due to the fact that there is relatively littledielectric in the final structure: (1) the average coefficient ofthermal expansion (CTE) of the space transformer layers is reduced to avalue closer to that of the metal than the dielectric, providing abetter match for the substrate CTE, especially if this is a ceramic, Si,etc; (2) dielectric materials with poorer mechanical properties (e.g.,photoresist) can be used successfully, since the mechanical integrity ofthe structure derives largely from the metal; (3) heat can be moreeasily dissipated; (4) overall rigidity is increased; and/or (5) regionsof dielectric on a given layer are fewer and smaller, facilitatingsingle point diamond machining of the layer by (a) reducing the risk ofdelamination and with less need for ‘pinking’ and b) reducing the amountof Cu (or other metal) that must be removed by diamond machining (i.e.,most of the Cu that is removed is that which is over small regions ofdielectric). Pinking is explained more fully in U.S. Patent ApplicationNo. 60/574,733 entitled “Methods for Electrochemically FabricatingStructures Using Adhered Masks, Incorporating Dielectric Sheets, and/orSeed layers That Are Partially Removed Via Planarization”, filed byLockard et al., which is hereby incorporated herein by reference as ifset forth in full. Moreover, the solid block space transformer requiresformation and patterning of fewer small features on most layers.

FIGS. 11A-11K shows the process for fabricating an SBST on a substratewith vias, using a patterned polymer/non-planar seed layer/plated metalapproach. In FIG. 11A, a substrate 402 with vias 404 has been coatedwith a polymer 406 to a thickness greater than the desired layerthickness. In FIG. 11B, the polymer has been patterned. In FIG. 11C,interconnect material 412 (e.g. Cu) has been deposited by PVD(preferably sputtering) or the like. If necessary for adhesion or as abarrier layer (e.g., in the case of polyimide) to Cu migration, Ti or Crcan be deposited before the Cu. If Ti or Cr is used as a barrier layer,since there won't be any on down-facing polymer surfaces over Cu, thenCu diffusion may still occur in an upward direction. This be managed ina variety of ways, for example, by providing extra space betweenhorizontal portions of the interconnects.

In FIG. 11D, interconnect material (e.g. Cu) 412 has been plated to athickness greater than the desired layer thickness. In FIG. 11E, thelayer has been planarized, preferably by diamond machining or possiblylapping.

In FIG. 11F, the previous operations have been repeated to fabricate asecond layer. In FIGS. 11G-11I, the previous operations have beenrepeated to fabricate a third layer. FIG. 11J depicts the state of theprocess after forming the 4^(th) through 7^(th) layers where the lastlayer is formed with a capping of gold or other metal that is resistantto Cu etching (assuming the interconnect material is copper and such abarrier is necessary). The deposition of the last layer may occur by acombination of patterning, sputtering, plating, and planarization. It isdesirable to avoid the use of copper on the last layer in thoseembodiments where copper will be placed above the space transformer(e.g. as a sacrificial material that surrounds probes that will bebonded to the space transformer) and then etched away. It should benoted that the seed layers shown explicitly in FIGS. 11D-11I have beenremoved from view in FIGS. 11J and 11K for simplicity.

Finally, in FIG. 11K, the space transformer has been diced from a largerwafer and a patterned passivation layer has been added to protect theshielding material (e.g. Cu) particularly along the sidewalls. Thispassivation layer may be used to protect the copper in the spacetransformer from an etchant that may be used to remove a sacrificialcopper material from probe structure that may be formed on the spacetransformer or bonded to the space transformer. If desired a gold capmay then be added (e.g., by plating) over the interconnect region(s) inorder to reduce the depth of the pad within the passivation. Thepassivation (e.g., photopatternable BCB) may be the same polymer that isused to fabricate the layers or a different one, as long as it isresistant to the Cu etchant. If applied as shown, since the passivationalso coats the polymer from which the layers are formed, then thispolymer (e.g., polyimide) can be of a type that is not very resistant toattack by the Cu etchant. It is also possible, since the Au layerprotects the Cu from above, to protect the sidewalls using anon-patterned material simply applied to the sidewalls as shown in FIG.12.

FIGS. 13A-13X depict schematic representations of side views of variousstates of a process according to a first embodiment of the inventionwhich calls for the co-fabrication of a set of microprobes and a spacetransformer which can be mounted to a PCB.

FIG. 13A depicts the state of the process after a dielectric (e.g.,alumina) substrate 102 is supplied having an array of relatively coarseconductive vias 104 which are composed of a metal that connects the top108 and bottom surfaces 106 of the substrate. The vias are shownproceeding straight from the bottom surface 106 of the substrate to thetop surface 108. In some variations of this embodiment, a circuitousroute may be taken by the vias. This embodiment of the invention uses a‘standard’ via substrate having vias in an array at a specific,relatively coarse pitch that is compatible with PCB line widths. Thecustomization offered by the present embodiment, is accomplishedentirely by the deposited layers of material. Typically some viasthrough the substrate will be used while others will remain unuseddepending on the specific layout of a particular space transformer. Thesubstrate of the present embodiment is thick and rigid enough to beself-supporting, while in variations of this embodiment the substratemay be flexible. Since the total thickness of the layers to be depositedis typically only on the order of several hundred microns, the substrateprovides the rigidity and robustness required for mounting the finalspace transformer and microprobe combination onto a PCB. As indicated,the substrate is metallized by deposition of a metal film 110 (e.g., bysputtering). The metal film 110 serves as a seed layer, as an adhesionlayer (if necessary), possibly as a barrier layer and/or as a transitionlayer. In some embodiments the metal film 110 may actually comprise twoor more individually applied layers, for example, the film may includean adhesion layer of, e.g., Ti, and a seed layer of, e.g., Au.

In FIG. 13B, a photoresist 112 has been applied and patterned and afirst layer of structural material 114 (e.g. Ni) has beenpattern-plated. In some alternative embodiments, sacrificial materialmay be pattern plated and then structural material may beblanket-plated, and then the layer planarized. Electrical contact (i.e.cathodic contact) may be made via the metal film 110.

In FIG. 13C, the resist has been stripped and the exposed portion ofmetal film 110 etched back. The portion of the film located under thedeposited structural material 114 is not removed as it is not readilyaccessible.

In FIG. 13D, a seed layer of sacrificial material 118 (e.g. Cu) has beendeposited by PVD (e.g., sputtering) over a thin deposition of anadhesion layer material 116 (e.g., Ti—W). This seed layer serves as acathode for subsequent plating and may be used as the contact point forconnecting to an electric circuit or alternatively some other conductiveelement connected to the seed layer may be used as the circuit contactpoint.

In FIG. 13E, the seed and adhesion layers are shown as having beenetched away from an area of an end-point detection region 122(additional end point detection pads may exist on the substrate but arejust not visible from the view provided by FIG. 13E. This removal may,for example, occur by use of a patterned mask that is formed after whichetching is allowed to occur, and then the mask removed. This removal ofthe seed layer prevents metal from being plated up in this region. Ofcourse, in practice the end point detection region 112 will need to bewide enough so that plating of metal occurring via a mushrooming effectfrom the side walls of structural material 112 which surrounds end-pointdetection pad 122 will not result in the covering of the pad. Inalternative embodiments, at the time of application of seed layer andadhesion layer material the end-point detection region may be shieldedso as to not receive the materials.

In FIG. 13F, a sacrificial material 124, e.g. Cu, has been thicklyplated (e.g. at greater than a desired layer thickness). In FIG. 13G thebuild has been planarized, completing the first layer. Building is thenallowed to continue so that additional layers are formed so long as bothstructural and sacrificial materials are conductive there is no need toapply a seed layer during formation of the 2^(nd)-N^(th) layers. If oneof the materials is non-conductive formation of some or all layers mayrequire use of one or more seed layers. In FIG. 13H, all the layers ofthe space transformer portion of the build have been completed withthree-dimensional structural material 114 interconnect being embedded insacrificial material 124 and laid out in a pattern that connects therelatively coarse-pitch vias to the relatively fine-pitch probes whichare still to be fabricated. In alternative embodiments masking could beapplied and selective deposition of dielectric made to occur (e.g. apattern that holds the extended interconnect lines in position).

In FIG. 13I, structural material 114 has been pattern-plated to formwhat will become fine-pitch vias which will extend through an insulatinglayer that will next be fabricated. In FIG. 13J, a cap 126 has beenapplied over the endpoint detection region or area and ahigh-temperature resistant dielectric material 128 (e.g., polyimide,glass, or the like) has been applied and (if needed) cured.

In FIG. 13K, the cap has been removed and the build has been planarized(and if necessary the opening 132 above the end-point detection pad hasbeen cleaned of debris from the planarization operation. Theplanarization operation removes the dielectric that lays over thestructural material vias of FIG. 13I and leaves in place a dielectriclayer that will form a ‘roof’ for the space transformer portion of thedevice. In some variations of the embodiment, if the cap is designed tobe flush or below flush with the surface of the vias afterplanarization, it need not be removed at this point. This may bedesirable since a cap will be again be used as indicated in FIG. 13M.

In FIG. 13L, a structural material, e.g. Ni, has been pattern-plated(e.g. via a patterned photoresist that is not shown) to form posts thatcontinue the fine-pitch vias and which will serve as the bases forprobes structures that will be formed. In variations of this embodiment,the posts may be formed without need for a patterned mask as the onlyconductive locations on the previous layer are the vias. Formation ofposts without a patterned mask may result in widening of the posts, dueto mushrooming, and in the posts having non-vertical sidewalls.

In FIG. 13M, another cap 134 has been applied to the endpoint detectionarea (unless the original cap has been left intact) and a seed layer 136of sacrificial material, e.g. Cu, and if needed an adhesion layer 138,e.g. of Ti—W, have been deposited by, for example, PVD. In FIG. 13N, asacrificial material 140, e.g. Cu, has been plated above the seed layerand in FIG. 13O, the build has again been planarized. The build is nowready for the fabrication of the probes.

In FIG. 13P, the probes 142(a)-142(c) have been electrochemicallyfabricated from a desired material along with an etch-proof shell ofstructural material 144 that encloses that probes and the sacrificialmaterial 140 that surrounds them. In variations of the presentembodiment, instead of forming a roof on the shell of structuralmaterial, a coating may simply be applied to prevent etching of thesacrificial material in the probe portion of the structure during anetching operation that removes the other regions of sacrificial materialas will be discussed in association with FIG. 13S. In some embodiments,it is desirable not to etch the sacrificial material in the probe regionprematurely. Since, for example, once the structure is released it maybe too weak to properly support the interconnects during infiltration ofa dielectric material (e.g. an epoxy) around the structural materialinterconnects of the space transformer which have been released fromsacrificial material as will be discussed in association with FIG. 13Uand since, for example, the presence of the sacrificial material in theprobe region may protect the probes from dicing debris that may begenerated in a subsequent operation. The electrochemical fabrication oflayers of the space transformer and of the probes is completed but theformation process as a whole is not yet completed.

In FIG. 13Q, a photoresist 152 has been patterned on the underside ofthe substrate 102, electrical (i.e. cathodic) contact has been made tothe plated or PVD-deposited material, and solder 154 (e.g., Sn—Pb) hasbeen plated onto the coarse vias (both used and unused, if desired). Asshown in FIG. 13R photoresist 152 has been removed and the solder isreflowed to form bumps (if desired). In variations of this embodiment,the solder bumping may be performed at an earlier stage of the process(e.g., after the metallization operation shown in FIG. 13A. In thepresent process, however, the bumping was not performed earlier, as thelack of the presence of bumps allowed for the bottom of the substrate toremain substantially flat during the EFAB process without need foradditional coating and planarization operations and the like. Since thesacrificial material has not yet been etched from the space transformerportion of the build, electrical contact to all coarse vias exists andso bumping of all vias can occur (even to unused vias) if desired.

In FIG. 13S, the exposed sacrificial material has been removed topartially release the structure (with the exception of the sacrificialmaterial that surrounds the probes which is protected by the shell ofstructural material surrounding it and by the dielectric roof of thespace transformer portion of the build. As a result, the removal of thesacrificial material may occur by immersing the entire build intosacrificial material etchant. The release occurs substantially in alateral manner, with etchant flowing under the roof and aroundstructural material interconnects and structural material pillars 162that may be used to support the roof of the space transformer (e.g., onein each corner of the device, or spaced out at intervals around theperimeter). It may be necessary, however, to coat the solder bumps witha protective coating if it is attacked by and exposed to the sacrificialmaterial etchant. Following etching of the sacrificial material (andremoval of the protective coating from the solder if previouslyapplied), diffusion bonding (e.g., at 250° C.) may be performed toimprove the inter-layer adhesion of the device. More teaching concerningthe use of diffusion bonding in electrochemical fabrication processesmay be found in U.S. patent application Ser. No. 10/841,384 which isfiled May 7, 2004 by Cohen et al. which is entitled “Method ofElectrochemically Fabricating Multilayer Structures Having ImprovedInterlayer Adhesion” and which is hereby incorporated herein byreference as if set forth in full.

In some variations of the present embodiment, reflow of the solder maynot have occurred prior to diffusion bonding and the diffusion bondingmay serve to reflow the solder. In some embodiments, it may be desirableto perform diffusion bonding after release of the space transformerinterconnects from the sacrificial material, particularly when thesacrificial material and the structural material have a significantdifference in their coefficients of thermal expansion as may be the casefor a nickel structural material and a copper sacrificial material.

In FIG. 13S, a coating 166 has been applied to prevent depositing ofspace transformer backfill polymer (e.g. a low-viscosity epoxy) onto thebumps. In variations of this embodiment the coating may be appliedearlier if it is capable of withstanding the temperatures associatedwith diffusion bonding. In some variations of the present embodiment,the coating 166 covering the bumps may be eliminated if the backfillpolymer is applied in such a way so as to avoid the backfill materialcontacting the bumps. FIG. 13U shows the state of the process after theback fill material 172 has been infiltrated into the structure and curedto fill the voids in the space transformer. In the present embodimentthe epoxy material is allowed to fill all exposed openings. Invariations of the embodiment, further restrictions on accessibility ofthe backfill material to certain regions may be implemented. Since theinterconnects are fastened at both ends, it is believed that, withcareful backfilling, they will be able to resist deformation andshorting to one another during the filling process. As shown in FIG.13U, some epoxy has also coated over the top of the device which can beremoved by a planarization operation, as shown in FIG. 13V, along withthe top of the structural material shell that protected the sacrificialmaterial located in the probe region (as shown in FIG. 13V.

In FIG. 13W, the build has been diced to allow separation of individualpackage dies. In this embodiment, dicing occurs prior to release of theremaining sacrificial material and thus dicing occurs while the entirestructure is either embedded in sacrificial material (probe portion) orepoxy (space transformer portion). After dicing, debris is removed(e.g., by megasonic or ultrasonic cleaning). In variations of thepresent embodiment, dicing may occur after release of the probes fromthe sacrificial material. The dicing is performed so that it removes thesidewalls of the Ni shell in the probe region so that the existence ofthe shell does not limit the accessibility of the probes and a circuitelement to be contacted by them when put to use. As shown, the dicingmay leave behind a portion of the Ni pillars (in the transformerregion), whereas in variations of this embodiment, the pillars may beremoved in their entirety or left in their entirety.

FIG. 13X, depicts the state of the process after the bottomside coating(and any overlying epoxy) have been removed and the remainingsacrificial material removed to release the probes. The probe/spacetransformer package is now ready to be mounted to a printed circuitboard, PCB, (e.g., using surface mount techniques) or to any otherdesired component. An underfill material may be used to fill any spacebetween the package and the PCB after bonding of the package to the PCB(i.e. via reflow of the solder bumps). It may be desirable to avoiddamage to the device, and assuming the PCB can tolerate the sacrificialmaterial etchant, it may be desirable to mount the device to the PCBfirst, and then perform the final sacrificial material release.

In an alternative embodiment, in lieu of application of a dielectricmaterial 128, as applied in FIG. 13J, a thin metal layer may be usedthat is capable of being later etched. For example, such etching mayoccur after the release of the remaining sacrificial material in FIG.13X to avoid shorting the probes together. Sn, Ni, and Au are examplesof metals that may be considered for this use.

FIGS. 14A-14G provide various perspective, side and close up views of anexemplary conceptual space transformer and probe array that may beformed with some embodiments of the invention wherein the spacetransformer is shown as free standing (i.e. not encapsulated in adielectric). In some embodiments, the space components of the spacetransformer may be encapsulated in a dielectric or in a combination ofdielectric embedded in a conductive material. The substrate of the spacetransformer may be bonded to a PCB, interposer, backing board, or thelike. Probes may be formed directly on the space transformerinterconnects or they may be transferred and bonded to the spacetransformer singly or in one or more multi-probe arrays. In someembodiments, different substrates may be used, for example, instead ofthe substrate feeding its vias straight from one surface to an opposingsurface they may be fed from one surface to a perpendicular surface(e.g. from a top surface to one or more of the sidewalls).

FIG. 14A provide a side view of a sample space transformer 502 having asubstrate portion 504, an interconnect and component region 506, andhaving a probe array 508 attached to its upper surface. To see thevarious interconnects and components located within the space transform,it is depicted without any encapsulating material. FIGS. 14B and 14Cprovide a distance and close up perspective views of the spacetransformer and probes. Various components and features of the probesand space transformer can be seen: (1) inductors 512; (2) capacitors514; (3) ground planes and power planes 516; (4) vias with varyingcross-sectional dimensions (i.e. elements that run in essentially adirection perpendicular to the plane of the substrate) 522, 524, and526; (5) traces with varying widths and heights (elements running inessentially a direction that is parallel to the substrate) 532, 534, and536; and (6) probes with different diameters and different tips 542 and544. As can also be seen trace positions and via positions are notlimited to separate layers as is typical for commercial spacetransformers (i.e. horizontal traces and vertical vias may coexist onthe same layers). FIG. 14D shows another perspective view of the spacetransformer which allows a via 562. FIGS. 14E and 14F provide furtherclose up perspective views of probes and space transformer components.FIG. 14G provides a close up view that allows coaxial interconnectstructures 572 in the space transformer to be seen.

In some embodiments of the invention, the structural material chosen foruse in the space transformer portion of the build need not be the sameas that chosen for the probe portion; material used in the spacetransformer may best be optimized for high conductivity and does notnecessarily need to meet stringent mechanical specifications for yield,fatigue, etc. as does the material used for the probes themselves. ThusAu or Cu might be a desirable structural material for the interconnectsof the space transformer region while Ni, Ni—Co, or NiP may be moredesirable for the probes.

In still embodiments of the invention, the interconnects in the spacetransformer may be formed not simply as conductive traces but instead asconductive traces with shielding conductors (e.g. like coaxial lines)that may be useful in high frequency applications and the like. Similarshielding may exist around the individual probes (as part of the probedesign) and may be separated from the central conducting elements of theprobes by continuous or periodic locations of a desired dielectricmaterial. To aid in etching any sacrificial material and/or possiblerelease of a back filling material from between the central interconnectleads and surrounding shield material, the shield material may beperforated with holes that give reasonable access to an etchant.

In various embodiments of the invention, different planarizationoperations are possible. In some embodiments, e.g. on some layers in abuilding process, single stage lapping or multi-stage lapping may beused while in other embodiments, chemical mechanical polishing may beused, while in still other embodiments fly cutting, or diamondmachining, may be used. Further teachings about planarizing layers andsetting layers thicknesses and the like are set forth in the followingUS patent applications which were filed Dec. 31, 2003: (1) U.S. PatentApplication No. 60/534,159 by Cohen et al. and which is entitled“Electrochemical Fabrication Methods for Producing Multilayer StructuresIncluding the use of Diamond Machining in the Planarization of Depositsof Material” and (2) U.S. Patent Application No. 60/534,183 by Cohen etal. and which is entitled “Method and Apparatus for MaintainingParallelism of Layers and/or Achieving Desired Thicknesses of LayersDuring the Electrochemical Fabrication of Structures”. Furthermore, thetechniques disclosed explicitly herein may benefit by combining themwith the techniques disclosed in U.S. patent application Ser. No.11/029,220 filed Jan. 3, 2005 (now U.S. Pat. No. 7,271,888 issued Sep.18, 2007) by Frodis et al. and entitled “Method and Apparatus forMaintaining Parallelism of Layers and/or Achieving Desired Thicknessesof Layers During the Electrochemical Fabrication of Structures”(corresponding to Microfabrica Docket No. P-US132-A-MF). These patentfilings are each hereby incorporated herein by reference as if set forthin full herein.

In some alternative embodiments, the space transformer portion of thepackage may be formed directly with structural material interconnectsand with a dielectric support material instead of with a conductivesacrificial material or in addition to a conductive sacrificial materialthat may still be located in some areas. Various techniques forcombining conductive materials and dielectric materials inelectrochemical fabrication process, and possibility into the finalstructures as formed, are set forth in a number of patent applications:(1) U.S. Patent Application No. 60/534,184, by Cohen, which as filed onDec. 31, 2003, and which is entitled “Electrochemical FabricationMethods Incorporating Dielectric Materials and/or Using DielectricSubstrates”; (2) U.S. Patent Application No. 60/533,932, by Cohen, whichwas filed on Dec. 31, 2003, and which is entitled “ElectrochemicalFabrication Methods Using Dielectric Substrates”; (3) U.S. PatentApplication No. 60/534,157, by Lockard et al., which was filed on Dec.31, 2004, and which is entitled “Electrochemical Fabrication MethodsIncorporating Dielectric Materials”; (4) U.S. Patent Application No.60/574,733, by Lockard et al., which was filed on May 26, 2004, andwhich is entitled “Methods for Electrochemically Fabricating StructuresUsing Adhered Masks, Incorporating Dielectric Sheets, and/or Seed Layersthat are Partially Removed Via Planarization”; and U.S. PatentApplication No. 60/533,895, by Lembrikov et al., which was filed on Dec.31, 2003, and which is entitled “Electrochemical Fabrication Method forProducing Multi-layer Three-Dimensional Structures on a PorousDielectric”. The techniques disclosed explicitly herein may benefit bycombining them with the techniques disclosed in U.S. patent applicationSer. No. 11/029,216 filed Jan. 3, 2005 by Cohen et al. and entitled“Electrochemical Fabrication Methods Incorporating Dielectric Materialsand/or Using Dielectric Substrates” (corresponding to MicrofabricaDocket No. P-US128-A-MF) and U.S. Patent Application No. 60/641,292filed Jan. 3, 2005 by Dennis R. Smalley and entitled “Method of FormingElectrically Isolated Structures Using Thin Dielectric Coatings”(corresponding to Microfabrica Docket No. P-US121-A-MF). These patentfilings are each hereby incorporated herein by reference as if set forthin full herein.

Further teachings about microprobes and electrochemical fabricationtechniques are set forth in a number of US patent applications whichwere filed on Dec. 31, 2003. These filings include: (1) U.S. PatentApplication No. 60/533,933, by Arat et al. and which is entitled“Electrochemically Fabricated Microprobes”; (2) U.S. Patent ApplicationNo. 60/533,975, by Kim et al. and which is entitled “Microprobe Tips andMethods for Making”; (3) U.S. Patent Application No. 60/533,947, byKumar et al. and which is entitled “Probe Arrays and Method for Making”;and (4) U.S. Patent Application No. 60/533,948, by Cohen et al. andwhich is entitled “Electrochemical Fabrication Method for Co-FabricatingProbes and Space Transformers”. Furthermore, the techniques disclosedexplicitly herein may benefit by combining them with the techniquesdisclosed in U.S. patent application Ser. No. 11/029,180 filed Jan. 3,2005 by Chen et al. and entitled “Pin-Type Probes for ContactingElectronic Circuits and Methods for Making Such Probes” (Correspondingto Microfabrica Docket No. P-US139-A-MF); U.S. patent application Ser.No. 11/325,404 filed Jan. 3, 2006 by Chen et al. and entitled “VerticalMicroprobes for Contacting Electronic Components and Method for MakingSuch Probes” (corresponding to Microfabrica Docket No. P-US153-A-MF);U.S. patent application Ser. No. 11/029,217 filed Jan. 3, 2005 (now U.S.Pat. No. 7,412,767 issued on Aug. 19, 2008) by Kim et al. and entitled“Microprobe Tips and Methods For Making” (corresponding to MicrofabricaDocket No. P-US122-A-MF); U.S. patent application Ser. No. 11/028,958filed Jan. 3, 2005 by Kumar et al. and entitled “Probe Arrays andMethods for Making” (corresponding to Microfabrica Docket No.P-US123-A-MF); and U.S. patent application Ser. No. 11/029,221 filedJan. 3, 2005 (now U.S. Pat. No. 7,531,077 issued May 12, 2009) by Cohenet al. and entitled “Electrochemical Fabrication Process for FormingMultilayer Multimaterial Microprobe Structures” (corresponding toMicrofabrica Docket No. P-US138-A-MF). These patent applications areeach hereby incorporated herein by reference as if set forth in fullherein.

Some embodiments may employ mask based selective etching operations inconjunction with blanket deposition operations. Some embodiments mayform structures on a layer-by-layer base but deviate from a strictplanar layer on planar layer build up process in favor of a process thatinterlacing material between the layers. Such alternating buildprocesses are disclosed in U.S. application Ser. No. 10/434,519, filedon May 7, 2003, entitled Methods of and Apparatus for ElectrochemicallyFabricating Structures Via Interlaced Layers or Via Selective Etchingand Filling of Voids which is herein incorporated by reference as if setforth in full.

Some embodiments may not use any blanket deposition process and/or theymay not use a planarization process. Some embodiments may involve theselective deposition of a plurality of different materials on a singlelayer or on different layers. Some embodiments may use selectivedeposition processes or blanket deposition processes on some layers thatare not electrodeposition processes. Some embodiments may use nickel asa structural material while other embodiments may use differentmaterials. Some embodiments may use copper as the structural materialwith or without a sacrificial material. Some embodiments may remove asacrificial material while other embodiments may not.

Many other alternative embodiments will be apparent to those of skill inthe art upon reviewing the teachings herein. Further embodiments may beformed from a combination of the various teachings explicitly set forthin the body of this application. Even further embodiments may be formedby combining the teachings set forth explicitly herein with teachingsset forth in the various applications and patents referenced herein,each of which is incorporated herein by reference.

In view of the teachings herein, many further embodiments, alternativesin design and uses of the instant invention will be apparent to those ofskill in the art. As such, it is not intended that the invention belimited to the particular illustrative embodiments, alternatives, anduses described above but instead that it be solely limited by the claimspresented hereafter.

1. A fabrication process for co-fabricating a multi-layer probe arrayand a space transformer, comprising: (a) forming and adhering a layer ofmaterial to a previously formed layer and/or to a substrate, wherein thelayer comprises a desired pattern of at least one material; and (b)repeating the forming and adhering operation of (a) a plurality of timesto build up an array of probes and a space transformer from a pluralityof adhered layers, and wherein at least a portion of the plurality oflayers comprises at least one structural material and at least onesacrificial material; and (c) after formation of at least a plurality oflayers, subjecting the multi-layer structure to a release process thatremoves at least a portion of at least one sacrificial material from atleast some portions of some layers, wherein the space transformercomprise a plurality of interconnect elements that connect on one sideto probes that have a first averaged spacing and connect to pads onanother side that have a second averaged spacing that is greater thanthe first averaged spacing.
 2. The process of claim 1 wherein thefabrication process comprises an electrochemical fabrication process. 3.A fabrication process for fabricating a multi-layer space transformer,comprising: (a) forming and adhering a layer of material to a previouslyformed layer and/or to a substrate, wherein the layer comprises adesired pattern of at least one material; and (b) repeating the formingand adhering operation of (a) a plurality of times to build upconfiguration of conductive interconnect elements in a configuration ofa desired space transformer, wherein the plurality of layers are adheredto one another and comprise at least one of (i) at least one structuralmaterial and at least one sacrificial material or (ii) at least twostructural materials one of which is a conductor and one of which is adielectric.
 4. The process of claim 3 wherein the space transformer iscomprises metal electrodeposited or electroless deposited on a layer bylayer basis where the height of at least some layers is set by aplanarization operation that planarizes an interconnect material and atleast one other material.
 5. The process of claim 3 wherein the spacetransformer comprises vias and traces that coexist on at least somelayers.
 6. The process of claim 3 wherein the space transformercomprises at least one more coaxial interconnects.
 7. The process ofclaim 3 wherein the space transformer comprises interconnects havingtraces having at least two different widths.
 8. The process of claim 3wherein the space transformer comprises interconnects comprising viasthat have at least two different widths.
 9. The process of claim 3wherein the space transformer comprises interconnects have tracethicknesses that are at least as thick as some planarized thicknesses ofa dielectric material.
 10. The process of claim 3 wherein the spacetransformer comprises interconnects have trace thicknesses that are atleast as thick as the differential height between some interconnecttraces.
 11. The process of claim 3 wherein at least one layer of thespace transformer is formed using a process comprising: patterning afirst material, applying a non-planar seed layer, electrodepositing asecond material, and trimming off at least a portion of the depositedfirst material.
 12. A space transformer comprising a plurality ofinterconnect elements that are connectable on one side to probes thathave a first averaged spacing and connectable on a different side topads that have a second averaged spacing that is greater than the firstaveraged spacing.
 13. The process of claim 12 wherein the spacetransformer comprises metal electrodeposited or electroless deposited ona layer by layer basis where the height of at least some layers is setby a planarization operation that planarizes an interconnect materialand at least one other material.
 14. The process of claim 12 wherein thespace transformer comprises vias and traces that coexist on at leastsome layers.
 15. The process of claim 12 wherein the space transformercomprises at least one more coaxial interconnects.
 16. The process ofclaim 12 wherein the space transformer comprises interconnects havingtraces having at least two different widths.
 17. The process of claim 12wherein the space transformer comprises interconnects comprising viasthat have at least two different widths.
 18. The process of claim 12wherein the space transformer comprises interconnects have tracethicknesses that are at least as thick as some planarized thicknesses ofa dielectric material.
 19. The process of claim 12 wherein the spacetransformer comprises interconnects have trace thicknesses that are atleast as thick as the differential height between some interconnecttraces.